1. Field of the Invention
This invention relates generally to logic circuits combining TTL (bipolar transistor-transistor logic) stages with CMOS stages. More particularly, it relates to attempts to overcome the problems arising from mismatch between the amplitude of binary logic-high voltages for the two different types of stages. More particularly yet, it is directed at minimizing the leakage current (I.sub.cct) arising in CMOS gates controlled by TTL-stage outputs, the logic-high voltages of which are inadequate to completely turn off PMOS pullup transistors. Most particularly, it relates to BiCMOS I/O pins for latched or clocked parts, where inputs must always be active (available to receive data).
2. Prior Art
In recent years great improvements have been made in logic circuitry through the development of completely integrated BiCMOS circuits able to exploit the advantages specific to both CMOS logic circuits-high input impedance, low power demand--and bipolar (TTL) logic circuits-high current sourcing/sinking capacity and speed. One of the consequences of combining CMOS and TTL is that, at one or more points in the operating circuit, output from a TTL stage may be the input to a CMOS circuit, at which point the disparity between the binary logic-high voltages of CMOS and TTL circuits, respectively, can give rise to difficulties.
CMOS binary logic voltages range rail to rail, i.e. GND to V.sub.cc. For CMOS and BiCMOS circuitry, V.sub.cc is typically 5 volts so that, for CMOS circuitry, logic-low is typically 0 volts and logic-high is typically 5 volts. In contrast, logic-high for a TTL stage is typically V.sub.cc -2 V.sub.BE, where V.sub.BE is the voltage drop across a forward-biased p-n junction. Since V.sub.cc -2 V.sub.BE is insufficient voltage to turn off a PMOS pullup transistor coupled to the high voltage power rail, a problem arises when the output from a TTL stage is used to control (i.e., turn on and turn off) a CMOS stage. (With a V.sub.cc of 5 volts, V.sub.cc -2 V.sub.BE is generally around 3.4 volts; nevertheless, depending on temperature and/or specific TTL output stage design, it can actually be less than 3 volts.) Thus, when the input to a CMOS stage is TTL-stage output, a logic-high signal-which should turn on a pulldown NMOS transistor while turning off a pullup PMOS transistor-will do the former while only incompletely turning off the pullup transistor. This results in a wasteful leakage current from V.sub.cc to GND passing through the pullup and pulldown transistors. This can be appreciated by reference to FIG. 1 (Prior Art), which shows the output portion of a BiCMOS buffer to the left and a CMOS input stage of another subcircuit to the right. The output signal from the (boxed) Darlington Pair comprising the current-sourcing part of the output stage of the TTL circuit to the left becomes the input data signal for the CMOS stage to the right when the left circuit is in its active mode. Binary logic-high for TTL output is V.sub.cc reduced by the forward drop of two diodes, for reasons that can be seen from FIG. 1. I.e., when the two transistors of the Darlington Pair are both conducting, V.sub.out is connected to V.sub.cc across a conducting bipolar transistor coupled to V.sub.cc across a forward biased Schottky diode. The combined circuit depends on this logic-high output turning off the PMOS pullup transistor QPX and turning on the NMOS pulldown transistor QNX. However, with the source and substrate of QPX tied to V.sub.cc, as shown, the TTL logic-high signal (V.sub.cc -2V.sub.BE) will be insufficient to turn QPX completely off. It will, however, be sufficient to turn on QNX, with the result that there will be a coupling between V.sub.cc and GND through QPX and QNX while the TTL output/input is high. This wasteful leakage current is referred to by various names: "quiescent current," "static high current," and "static current I.sub.cct." Its magnitude depends upon the channel sizes of QPX and QNX. Since it may be occurring simultaneously in many CMOS input stages, it can reach very high levels, extending into the milliamp range.
There are several prior art approaches to resolving the I.sub.oct problem. Two involve modifying the CMOS input stage and then using a multi-CMOS-stage translating sequence, so that the TTL input signal can be translated ultimately into a CMOS logic output signal in spite of the modification of the input stage. For example, a reduction in the effective high potential rail for the CMOS input stage enables the TTL logic-high to completely turn off the pullup transistor of the input stage. The effective reduction in the high potential side of the input stage can be accomplished by interposing several forward-biased diodes between V.sub.cc and the source node (and the bulk) of the input pullup transistor-which results in the input stage being coupled between a high potential of V.sub.cc -2V.sub.BE and GND. With this expedient, a TTL high applied at the input is sufficient to completely cut off the input pullup transistor. The price paid, however, is that when a TTL low is input to the CMOS input stage, the resulting logic-high output to the next CMOS stage is only V.sub.cc -2V.sub.BE, and insufficient to turn off the pullup transistor of that next stage. In other words, the I.sub.cct problem has just been deferred from the initial CMOS stage to the next CMOS stage. (Because of performance specifications requiring that the ultimate output range is full rail-to- rail--GND to V.sub.cc --it is not possible to simply lower the voltage of the high potential rail for the entire CMOS buffer.) The fix is indeed to lower the high potential side of the second CMOS buffer, but not by a full 2V.sub.BE. For the CMOS stage after that, the high potential rail is then back to V.sub.cc or close to it. Unfortunately, the series of translating stages and the potential-lowering diodes used in this approach introduce serious delays, significantly increasing the propagation time between the initial input to the first stage of the buffer and the final output. This elimination of I.sub.cct has been achieved at the cost of increasing the propagation time T.sub.p.
The other prior art "sequential" approach is to accept a non-zero, though reduced, level of I.sub.cct in exchange for maintaining a better T.sub.p. The high potential side is left untouched and the I.sub.cct of the initial stage is reduced by reducing the channel width of the input pulldown transistor. This ensures a small I.sub.cct in the CMOS input stage and also a full-scale logic-high output from this first stage. The problem created by this approach is that it is necessary to ultimately have large conduction channels in the pullup (and pulldown) transistors at the buffer output. Since it is impracticable to have a large channel width increase from one stage to the next, it is necessary to have a series of stages over which the width increases (by about a factor of three each time) until it is at the level required by the output stage. Consequently, the cost of dealing with I.sub.cct is again the need to have a sequence of CMOS stages. Furthermore, in this approach, I.sub.cct leakage has not been eliminated-only reduced, a residual I.sub.cct being accepted in a tradeoff for tolerable T.sub.p.
An additional prosaic prior art approach to the I.sub.cct problem is to modify the TTL output stage, in a compromise intended to boost the TTL logic-high while still retaining some of the advantages of the bipolar output stage. It involves replacing the standard Darlington pair of bipolar transistors, in which by design the logic-high output is V.sub.cc -2V.sub.BE, with a single-transistor output. In order to compensate for the reduced current gain imposed by this change, the single transistor is chosen to be much larger than either of the two transistors in the Darlington pair. Even with this size increase, the output current available from this one-transistor stage is reduced considerably. (One problem is that the stage has a current gain of only .beta., compared with .beta..sup.2 for the standard Darlington pair.) More seriously, these modifications result in increased noise-associated in part with the need to discharge a much higher capacitive energy at the bipolar transistor junction with and in increased demands on the limited space available on the die.
A variant on the "V.sub.cc reduction" approach reduces the high potential rail for the first CMOS stage, then introduces a feedback transistor to effectively boost the logic-high output for that stage to V.sub.cc, thereby avoiding the use of a series of CMOS stages with varying logic-high levels. This approach is the subject of U.S. Pat. No. 5,087,841 (Rogers, 1992). As depicted in FIG. 2 (Related Art) with which sets out a circuit meant to receive TTL-stage output into V.sub.IN with the solution of Rogers is to combine the input-stage high-potential-rail reduction with a feedback loop. With the high potential rail for the input stage reduced to V.sub.cc -2V.sub.BE, the logic-high TTL output (V.sub.cc -2V.sub.BE) is sufficient to completely turn off the input-stage pullup transistor P1, eliminating I.sub.cct. On the other hand, when the input stage is turned on (by a logic-low TTL signal at V.sub.IN) P1 outputs a logic-high of only V.sub.cc -2V.sub.BE, which turns on the second-stage pulldown transistor N2 but is insufficient to completely turn off the second-stage pullup transistor P2. Nevertheless, once pulldown transistor N2 is turned on, the second stage output V.sub.2 is pulled to ground and the feedback connection from that output back to the control node of the PMOS feedback transistor QF turns QF on and boosts the input signal to the second stage up to V.sub.cc, resulting in P2 being turned off completely. Thus, in contrast to the circuit without the feedback transistor, where the reduced logic-high output from the input stage is unable to completely turn off the pullup transistor of the second stage--thus deferring the I.sub.cct leakage to that point--the design set out in FIG. 2 both eliminates I.sub.cct from the first stage--by lowering the high potential power rail voltage for that stage--and turns off the second stage pullup transistor completely. Unfortunately, for those applications which need extreme speed the 0.5 nsec or so lag time caused by the two junctions interposed between the high-potential power rail and the input stage stage is intolerable.
What is needed, then, is a method of completely eliminating I.sub.cct while: (1) not sacrificing T.sub.p, (2) introducing no additional noise, and (3) not changing the structure of the TTL output stage.